Designation: Engineer- IC Design
Eligibility: Bachelor's/Master's Degree
Be responsible for ASIC physical design (Block level Place & Route) for large-scale/low-power/high-performance chips.
- Bachelors or Master’s degree in Electrical/Electronics and communications/Computer Engineering with 0-2 years of related experience.
- Candidate must hold Diploma or PG diploma in VLSI physical design course from any of the reputed VLSI training institutes.
- Fluent with Netlist-to-GDS flow using any of the industry standard EDA tools from Sysopsys/Cadence/ATOPTECH.
- Hands-on experience in complete block P&R flow in 40/28nm (and/or below technology) is a plus.
- Knowledge in Performance, Power, Area and clock methodology.
- Experienced in Tcl/Perl scripting to innovate P&R methodology.
- Must be able to work independently, and be flexible to take challenging assignments.
- Must have good communication skills, and can take tapeout pressure.
Experienced in any of the following is a plus:
1. TSMC 20/16nm technology
2. Low power implementation
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